1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device used for controlling power consumption of an IC on which a high-resistance load type static RAM and a logic circuit are mounted.
2. Description of the Related Art
Conventionally, memory cells of a high-resistance load type static RAM, i.e., an E/R type static RAM (Enhancement/Resistor type static RAM to be referred to as "E/R type SRAM" hereinafter) have a circuit arrangement, e.g., shown in FIG. 1. Referring to FIG. 1, reference symbol V.sub.DD denotes a positive power source voltage; V.sub.SS, a ground power source voltage; R, a high-resistance load; Tr1 and Tr2, transferring gates constituted by n-channel MOS transistors; Tr3 and Tr4, driver transistors constituted by n-channel MOS transistors; B and B, bit lines; and W, word lines.
In general, the high-resistance load R used in the memory cell of the E/R type SRAM is constituted by a second polysilicon layer to decrease an area occupied by the memory cell. This can be achieved by a two-layer polysilicon technique in which the gate electrodes of the MOS transistors are constituted by a first polysilicon layer, and the high-resistance load R is constituted by the second polysilicon layer. In addition, in the high-resistance load type cell, since a data retention current (standby current, to be referred to as "leakage current" hereinafter) I.sub.R is changed according to the resistance of the high-resistance load R, the resistance generally has a large value.
As the first characteristic of the E/R type SRAM, the E/R type SRAM is integrated at a high density. When the two-layer polysilicon technique is used, as described above, the first polysilicon layer is used as the gate electrodes of the MOS transistors Tr1 to Tr4, and the high-resistance load R can be formed by the second polysilicon layer formed on the MOS transistors Tr1 to Tr4. As the second characteristic, a relatively small leakage current I.sub.R can be obtained by a technique for increasing the resistance of the polysilicon layer. Therefore, in the above load cell, it is generally advantageous that the load R has a resistance as high as possible. Note that, at present, an increase in resistance of the load R is a required condition for obtaining a large-capacity memory. For example, in a 1-Mbit SRAM, in order to obtain a leakage current I.sub.R of several .mu.A (micro ampere), each memory cell is required to have a load resistance of several tera ohms (10.sup.12 .OMEGA.) or more. However, in consideration of a margin in the actual manufacture, a resistance of several tera ohms or more is difficult to always obtain, and the leakage current I.sub.R has variations in the range of several .mu.A to several hundred .mu.A, i.e., the maximum variation being hundred times or more the minimum variation.
In a semiconductor memory device on which an E/R type SRAM and a logic circuit are mounted, as shown in FIG. 2, power source voltages V.sub.DD and V.sub.SS of a logic section 11 and power source voltages V.sub.DD and V.sub.SS in a memory section 12 of the E/R type SRAM are generally applied from the same power source pads 13a and 13b. Therefore, when the power consumption of a semiconductor chip 14 is evaluated, the power consumption of all the E/R type SRAM and the logic section must be evaluated. A total current is evaluated at present.
For example, in the semiconductor chip 14 on which a large-capacity E/R type SRAM and a logic section are mounted, a variation in the leakage current I.sub.R from a memory section 12 of the E/R type SRAM is larger than that of a leakage current from the logic section 11. That is, when a total leakage current of the semiconductor chip 14 is evaluated, since the static current consumption of the logic section 11 is generally about 100 .mu.A, the leakage current from the logic section 11 and a current obtained by varying the leakage current I.sub.R from the memory section 12 of the E/R type SRAM cannot be distinguished from each other.
Note that the logic section 11 and the memory section 12 of the E/R type SRAM have different device arrangements, and a defective device may be formed in manufacturing. The logic section 11 and the memory section 12 must be independently discriminated from each other. Therefore, the independent discrimination of errors of leakage currents from the logic section 11 and the memory section 12 of the E/R type SRAM is one of the important factors. However, in a conventional circuit arrangement, this independent discrimination cannot be performed.
As described above, in a conventional semiconductor memory device, although the independent discrimination of errors of the leakage currents from the logic section and the memory section of the E/R type SRAM is important, it cannot be performed, resulting in inconvenience.